The present invention relates to the layout of a high-density SRAM which can be suitably used for suppressing the decrease in yield.
There has been a tendency such that even a layout margin must be reduced with the increase in the integration scale of SRAM (Static Random Access Memory). Particularly, a large number of memory cells are arranged in a matrix form, and therefore SRAM is designed so as to scale down individual memory cells in area to the absolute extent possible.
JP-A-2010-166102 discloses a group of SRAM memory cells designed in layout so that a word line and a VSS source line are arranged in different wiring layers and cross each other at right angles. In this case, the word line and VSS source line never extend in parallel over a long distance in a common wiring layer and therefore, the increase in the parasitic capacitance between wiring lines can be suppressed, and the decrease in the yield result from a failure of short circuit caused by a particle extending athwart the two wiring lines can be prevented.
To facilitate further downsizing without increasing the number of wiring layers, the layout margin must be reduced. For instance, with a through-hole via, hereinafter referred to as “via” simply, for connecting between wiring layers, a layout rule of making a wiring layer larger than a via has been adopted conventionally in consideration of the alignment accuracy in a photolithography process. However, a layout rule of permitting the width of a wiring layer as large as the size of a via has been also adopted for high-density SIAM cells. In this case, an end of a wiring line is disposed in line with an end of a via. Therefore, an alignment deviation brings about a condition which is referred as “misalignment” or “gap creation”, in which a via is formed where no wiring line is located.
JP-A-2003-303881 points out a problem arises between an aluminum wiring line and a via having a tungsten plug in a case such that the misalignment is allowed, and discloses a semiconductor manufacturing process to solve the problem. In the tungsten plug, a barrier film constituted by a titanium film for covering the bottom of the via, and the side wall thereof, and a titanium nitride film is formed. The reason for making this arrangement is to prevent the occurrence of a void as a result of the production of aluminum fluoride owing to a reaction between tungsten hexafluoride used in CVD (Chemical Vapor Deposition) of tungsten, and aluminum. In the state of the misalignment, the aspect ratio of the via becomes higher, which makes difficult to form a titanium/titanium nitride multilayer film serving as a barrier film of the plug on the side wall of the through-hole, and the aluminum of the wiring layer is left bared. Thus, the aluminum reacts with the tungsten hexafluoride where a sufficient barrier film is not formed, thereby producing a void, which poses problems such as the deterioration in the reliability of electrical connection between the plug and the wiring line, and the rise in connection resistance arise (see Paragraph No. 0006 of JP-A-2003-303881). Further, in case that the barrier film does not have a sufficient titanium nitride film near the bottom of the via, so the barrier film is constituted by only the titanium film, and the titanium film reacts with the tungsten hexafluoride and disappears, resulting in the exfoliation in the titanium nitride film (see Paragraph No. 0007 of JP-A-2003-303881). To solve the problems, JP-A-2003-303881 discloses a step for forming, by e.g. a highly directional sputtering method, a titanium nitride film serving as a barrier film in a through-hole, wherein the bared wiring line side face is nitrified by means of exposure to a nitrogen-containing gas (see Paragraph Nos. 0043 to 0046 of JP-A-2003-303881). Even if aluminum is exposed from the side face of the wiring line, the portion so exposed has been already nitrified with aluminum nitride formed therein, and the aluminum of the wiring line is prevented from reacting with tungsten hexafluoride. Therefore, even the adoption of the layout rule which permits the misalignment never causes the drop of the yield.